Part Number Hot Search : 
NTE23 M5265 NJU6377G RN1011 MP3274AP PFS3502 M74VH F1002
Product Description
Full Text Search
 

To Download HI-8200 Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
  holt integrated circuits www.holtic.com general description the HI-8200 is a quad analog cmos switch fabricated with sili- con-on-insulator (soi) technology for latch-up free operation and maximum switch isolation. high voltage gate drive is en- tirely created on-chip enabling +/-12v switching range from a single 3.3v or 5v supply. these switches are ideally suited for applications demanding low switch leakage when the power pins are 0v. (-40c to +85c) and extended (-55c to +125c) tem- perature range options. at 25 c and with vdd from 3.0v to 5.5v, the switch resistance (ron) is typically 8 ron is independent of vdd. in a switch- ing range of -5v to +5v, the maximum deviation of ron from flat is less than 5%. these switches conduct equally well in either direction. power down and off state leakages are less than 10na maximum. charge injection is less than 10pc. switching times are typi- cally 180ns to the on state and 60ns to the off state. the on- board charge pump allows an on/off cycle time of 5khz for all four switches simultaneously before the switching range be- comes restricted. the HI-8200 provides four each normally open switches when the switch control inputs are low. the hi-8201 provides four each normally closed switches when the switch control inputs are low. the hi-8202 provides a combination of two normally closed and two normally open switches. industry-standard plastic package options include 20-pin tssop, 16-pin dip and 16-pin qfn. ceramic packaging is available on request. all three products are offered in both in- dustrial  features   cmos analog switches with up to +/-12v switching range from a single 3.3v or 5v supply low ron: 10 max at 25c robust cmos silicon-on-insulator (soi) technology switch nodes are open-circuit when chip is powered down soi switch isolation with 1na typical off leakage esd protection > 4kv hbm fast switching time with break-before-make low power extended temperature range (-55c to +125c)         pin configurations (top views) december 2012 (ds8200 rev. b) 12/12 HI-8200, hi-8201, hi-8202 quad 10 ohm +/-12v outside-the-rails analog switch with open circuit when power off 16 s1a 15 in1 14 in2 13 s2a s1b 1 v- 2 gnd 3 s4b 4 12 s2b 11 v+ 10 vlogic 9 s3b s4a 5 in4 6 in3 7 s3a 8 16-pin 5mm x 5mm chip-scale package (see page 6 for additional package configurations) HI-8200pcx applications      avionics data bus isolation sample-and-hold circuits test equipment communications systems in1 1 s1a 2 -3 s1b 4 v- 5 gnd 6 s4b 7 -8 s4a 9 in4 10 20 in2 19 s2a 18 - 17 s2b 16 v+ 15 vlogic 14 s3b 13 - 12 s3a 11 in3 20-pin tssop package HI-8200psx product options part type in1 switch 1 in2 switch 2 in3 switch 3 in4 switch 4 HI-8200 0 open 0 open 0 open 0 open 1 closed 1 closed 1 closed 1 closed hi-8201 0 closed 0 closed 0 closed 0 closed 1 open 1 open 1 open 1 open hi-8202 0 open 0 closed 0 closed 0 open 1 closed 1 open 1 open 1 closed
holt integrated circuits 2 HI-8200, hi-8201, hi-8202 signal function description in1 logic input HI-8200 and hi-8202 are normally open when input low s1a switch node switch 1 node s1b switch node switch 1 node v- cap - bulk storage capacitor. add 0.1uf ceramic capacitor to gnd. (20v or higher). gnd supply reference ground s4b switch node switch 4 node s4a switch node switch 4 node in4 logic input HI-8200 and hi-8202 are normally open when input low in3 logic input hi-8201 and hi-8202 are normally closed when input low s3a switch node switch 3 node s3b switch node switch 3 node vlogic supply 3.3v or 5.0v logic supply v+ cap + bulk storage capacitor. add 0.1uf ceramic capacitor to gnd. (20v or higher). s2b switch node switch 2 node s2a switch node switch 2 node in2 logic input hi-8201 and hi-8202 are normally closed when input low v+ and v- pins are to be used for connection of bulk storage capacitors and be loaded. note: only must not pin descriptions -18v -12v -6v 0v 6v 12v 18v  10  15  20  25  30  35  v switch v switch typical r as a function of v and temperature (10ma switch current, on switch v = +3.3v) supply t = +125c t = +25c t = -55c
holt integrated circuits 3 electrical characteristics , gnd = 0v. operating temperature range (unless otherwise noted). v = 3.3v or 5.0v logic parameter conditions figure min typ max unit symbol switch parameters switch resistance, r 12v > vs > -12v leakage - i 12v > vs > -12v 2 1 10 na logic inputs input high voltage v 75% v input low voltage v 25% v input current i 80k ohm pulldown vlogic = 3.3v 45 vlogic = 5.0v 65 supply operating range vdd 3.0 5.5 idd inputs static 2.5 dynamic parameters max vin on/off cycling fcycle any load 5 khz turn on time t 3 180 250 ns turn off time t break-before-make time t 4 40 80 ns charge injection q v =0v, r =0 25c 5 -20 pc off isolation r f = 1 mhz, 25c 6 65 db crosstalk c 25c 7 90 db capacitance c switch off, 25c 8 15 pf c switch on, 25c 9 60 pf charge pump power on tvon v+ and v- = +/-14.5v vlogic = 5.0v 10 10 ms 25c, 10ma 1 6 8 10 (open circuit and | | power down) a a i 0.5 a ogic v ogic operating current vlogic = 3.3v 1.0 ma vlogic = 5.0v ma 3 80 150 ns f = 1 mhz,   on swleak ih il ih on off d ss r r off on il vl vl HI-8200, hi-8201, hi-8202 note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings continuous power dissipation (ta=70c): so package (derate 6.7mw/c above 70c)...................696mw plastic dip (derate 10.53 mw/c above 70c) .................842mw thin qfn (derate 21.3mw/c above 70c) ...................1702mw storage temperature range: ......................................-65c to +150c soldering temperature: (ceramic)......................60 sec. at +300c (plastic - leads).............10 sec. at +280c (plastic - body) .....................+260c max. supply voltage, v .........................................................................7.0v switch current (either direction, dc) peak switch current (1 ms pulse, 10% duty cycle max.)..................100ma digital input voltage (in1-4):..................................... logic : .................................................20ma -0.3v to v + 0.3v operating temperature range: (industrial)..........................-40c to +85c (hi-temp) ........................-55c to +125c maximum junction temperature ........................................................175c logic (voltages referenced to gnd = 0v)
holt integrated circuits 4 figure 1 - on resistance figure 3. switching times v (hi-8201) in v out v (HI-8200) in 50% 50% t on t off 50% 90% test circuits HI-8200, hi-8201, hi-8202 + - v s i ds r=v/i on 1 ds v 1 figure 2 - off leakage + - v s i (off) s v d aa - + i (off) d + - v s 35pf 300  +3.3v v logic v + v- gnd 0.1 f v out sa sb sa sb sa sb in 50% 50% figure 4. break-before-make time delay (hi-8202) 35pf 300  +3.3v v logic v + v- gnd 0.1 f v out1 s1a s1b in s2a s2b v s1 v s2 v out2 300  35pf v in v out1 3.3v 0v 50% 50% v out2 50% 90% t d t d 50% 90% 0.1 f (20v) 0.1 f (20v) 0.1 f (20v) 0.1 f (20v)
holt integrated circuits 5 HI-8200, hi-8201, hi-8202 figure 5. charge injection v in v out + - v s c 10nf l +3.3v v logic v + v- gnd v out sa sb in  v out qc inj = l x ut  v o r s v s 50  +3.3v v logic v + v- gnd 0.1 f v out sa sb in figure 6 - off isolation v s 50  +3.3v v logic v + v- gnd 0.1 f sa1 sb1 in1 figure 7 - channel-to-channel crosstalk v out sa2 sb2 in2 50  nc v s +3.3v v logic v + v- gnd 0.1 f (20v) 0.1 f 0.1 f (20v) sa sb in figure 8 - off capacitance capacitance meter f=1mhz +3.3v v logic v + v- gnd 0.1 f sa sb in figure 9 - on capacitance capacitance meter f=1mhz 0.1 f (20v) 0.1 f (20v) 0.1 f (20v) 0.1 f (20v) 0.1 f (20v) 0.1 f (20v) 0.1 f (20v) 0.1 f (20v)
holt integrated circuits 6 HI-8200, hi-8201, hi-8202 figure 10. charge pump power on + - +3.3v +3.3v v logic v + v- gnd t=0 t=0 2ms 4ms 6ms 8ms 10ms -15v -10v -5v 0v 5v 10v 15v time in1 1 s1a 2 s1b 3 v- 4 gnd 5 s4b 6 s4a 7 in4 8 16 in2 15 s2a 14 s2b 13 v+ 12 vlogic 11 s3b 10 s3a 9 in3 16-pin dip package HI-8200pdx additional package configurations 0.1 f (20v) 0.1 f (20v)
holt integrated circuits 7 ordering information hi - 820x xx x x temperature range flow burn in -40c to +85c -55c to +125c no yes i m -55c to +125c no t part number t i m package description 16 pin plasti c5x5mm chip scale (16pcs1) (no m-flow, pb-free only) part number pc 20 pin plastic tssop (20hs) ps pd lead finish part number pb-free, rohs compliant f tin / lead (sn / pb) solder blank 16 pin plastic dip (16p) function quad switch, normally open part number 8200 quad switch, normally closed 8201 8202 quad switch, two normally open, two normally closed HI-8200, hi-8201, hi-8202
p/n rev date description of change ds8200 new 10/18/12 initial release b 12/18/12 clarify that v+/v- pins be loaded. used for connection of bulk storage caps. must not only a 10/22/12 remove 1mohm resistor to gnd from test circuits. correct typo in pin descriptions revision history holt integrated circuits 8 HI-8200, hi-8201, hi-8202
holt integrated circuits 9 HI-8200 package dimensions 16-pin plastic chip-scale package millimeters package type: 16pcs1 bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) top view bottom view electrically isolated metal heat sink on bottom of package connect to any ground or power plane for optimum thermal dissipation 5.00 0.05 (0.197 0.002) 5.00 0.05 (0.197 0.002) 3.38 0.05 (0.133 0.002) 3.38 0.05 (0.133 0.002) 0.75 0.05 (0.03 0.002) 0.025 0.025 (0.001 0.001) 0.203 (0.008) ref. 0.80 (0.031) bsc 0.30 0.012 0.05 ( 0.002) .50 0.05 (0.020 0.002) 0.20 (0.008) min. inches (millimeters) package type: 20hs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) 20-pin plastic tssop 0 to 8 pin 1 .0095 .0025 (.245 .055) .2555 .0035 (6.500 .100) .173 .004 (4.400 .100) .006 .002 (.145 .055) .036 .005 (.925 .125) .004 .002 (.100 .050) .018 - .029 (.450 - .750) .252 .006 (6.400 .150) detail a see detail a .026 (.650) bsc
holt integrated circuits 10 HI-8200 package dimensions inches (millimeters) package type: 16-pin plastic dip 16p 0.745 (18.923) 0.810 (20.574) 0.240 (6.096) 0.260 (6.604) 0.300 (7.620) 0.370 (9.398) 0.125 (3.175) 0.150 (3.810) 0.015 (0.381) 0.035 (0.889) 0.100 (2.54) bsc. 0.045 (1.143) 0.065 (1.651) 0.015 (0.381) 0.023 (0.584) 0.120 (3.048) 0.150 (3.810) 0.290 (7.366) 0.310 (7.874) 0.008 (0.203) 0.015 (0.381)


▲Up To Search▲   

 
Price & Availability of HI-8200

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X